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Data Sheet
I 2 C Read Operation
The read operation using the I 2 C interface of the ADE7880 is
accomplished in two stages. The first stage sets the pointer to
the address of the register. The second stage reads the content of
the register.
As seen in Figure 101, the first stage initiates when the master
generates a start condition and consists in one byte representing
the address of the ADE7880 followed by the 16-bit address of the
target register. The ADE7880 acknowledges every byte received.
The address byte is similar to the address byte of a write operation
and is equal to 0x70 (see the I 2 C Write Operation section for
details). After the last byte of the register address has been sent
and acknowledged by the ADE7880 , the second stage begins
ADE7880
with the master generating a new start condition followed by an
address byte. The most significant seven bits of this address byte
constitute the address of the ADE7880 , and they are equal to
0111000b. Bit 0 of the address byte is a read/write bit. Because this
is a read operation, it must be set to 1; thus, the first byte of the
read operation is 0x71. After this byte is received, the ADE7880
generates an acknowledge. Then, the ADE7880 sends the value
of the register, and after every eight bits are received, the master
generates an acknowledge. All the bytes are sent with the most
significant bit first. Because registers can have 8, 16, or 32 bits,
after the last bit of the register is received, the master does not
acknowledge the transfer but generates a stop condition.
15
8
7
0
S 0 1 1 1 0 0 0 0
SLAVE ADDRESS
MOST SIGNIFICANT
8 BITS OF REGISTER
ADDRESS
LESS SIGNIFICANT
8 BITS OF REGISTER
ADDRESS
ACK GENERATED
BY ADE7880
ACKNOWLEDGE
GENERATED BY
MASTER
31
24
23
16
15
8
7
0
S
0
1
1
1
0
0
0 1
S
SLAVE ADDRESS
BYTE 3
(MOST SIGNIFICANT)
OF REGISTER
BYTE 2 OF
REGISTER
BYTE 1 OF
REGISTER
BYTE 0
(LESS SIGNIFICANT)
OF REGISTER
ACK GENERATED
BY ADE7880
Figure 101. I 2 C Read Operation of a 32-Bit Register
15
8
7
0
S 0 1 1 1 0 0 0 0
SLAVE ADDRESS
MOST SIGNIFICANT
8 BITS OF REGISTER
ADDRESS
LESS SIGNIFICANT
8 BITS OF REGISTER
ADDRESS
ACK GENERATED
BY ADE7880
ACKNOWLEDGE
GENERATED BY
MASTER
31
24
7
0
31
24
7
0
S 0 1 1 1 0 0 0 1
S
SLAVE ADDRESS
BYTE 3
(MOST SIGNIFICANT)
OF REGISTER 0
BYTE 0
(LESS SIGNIFICANT)
OF REGISTER 0
BYTE 3
(MOST SIGNIFICANT)
OF REGISTER 1
BYTE 0
(LESS SIGNIFICANT)
OF REGISTER n
ACK GENERATED
BY ADE7880
Figure 102. I 2 C Read Operation of n 32-Bit Harmonic Calculations Registers
Rev. A | Page 75 of 104
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